With a SCK & !SDO & PWM formula we can get the WS281x logical zeroes waveform: SCK & !SDO & PWM Waveform The idea is to send your data to the SPI interface and using the CLC logic with help of the PWM and timer to clock this data ones and zeros to the WS281x signal. ![]() To implement this approach you PIC needs to have free to use following 4 peripherals: a timer, PWM, CLC logic and a SPI interface. It uses the PIC16F1509 but we will use only its generic parts. From multiple source I found regarding this issue the Application Notes AN1606 may be worth mentioning. Composition of 24bit data of one GRB encoded LED The Hardware ApproachĪs discussed above we are considering only the hardware approach due to its reliability and lower requirements on the PIC. The LED will keep their configuration until a new configuration will be send. It is important that there are no pauses between the blocks since those may be considered RET codes and thereby reseting the sequence.Īfter we sent our data we leave the data line on low-voltage reseting the sequence. The we sent 10 (LEDs) * 24 (8bit G + 8bit R + 8bit B) bits right after each other without any pauses (see timing above) setting every of the 10 LEDs in our strip. Therefore if no change is necessary we just leave the data line on low voltage. There is no limitation on how long we can stay in reset sequence. We always start with low on the data line for more than 50us and by that sending the RET code. The one I was using uses the GRB order but this may differ. Look at the color order of the specific WS281x circuit. EncodingĮncoding the color code of multiple LEDs works by sending a 24bit number for each LED over the data line. This is an important observation when it comes to the implementation below. One may say that if the high voltage part is longer than half of the period than it is considered as logical “1”, if the high voltage part is shorter than half of the period than its considered as logical “0”. But the T0H/T0L and T1H/T1L ratio is a bit more open. Mainly there must be no longer interruptions between codes due to the RET code. The period is one of those timings which needs to be held up precisely. What can be found is that there are some timings which needs to be held up precisely and some do not. Any low voltage signal over Treset = 50us is considered the RET code. After a low voltage time follows on the data line filling the 1.25us period: in case of a logical “0” the T0L = 0.85us (+/- 150ns) and in case of logical “1” the T1L = 0.45us (+/- 150ns). In case of a logical “0” the T0H = 0.4us (+/- 150ns) and in case of a logical “1” the T1H = 0.8us (+/- 150ns). A logical value always starts with high voltage time on the data line. ![]() The 300ns tollerance is very important and a reason why the software approach fails very fast. ![]() The period of a logical value is 1.25us (+/- 300ns). 0 code encodes a logical “0”, 1 code encodes a logical “1” and RET code encodes a reset sequence. The WS281x implements 3 timings: 0 code, 1 code and RET code. Since we have only one data line we have to rely on timing. As already mentioned the biggest challenge is the timing protocol of the WS281x.
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